UCC3808-2

Features:

`Dual Output Drive Stages in Push-Pull Configuration
`130-A Typical Starting Current
`1-mA Typical Run Current
` Operation to 1-MHz
`Internal Soft Start
`On Chip Error Amplifier With 2-MHz Gain Bandwidth Product
`On Chip VDD Clamping
`Output Drive Stages Capable Of 500-mA Peak Source Current, 1-A Peak Sink Current


Pinout




Specifications

Supply voltage (IDD 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .  20 mA
OUTA/OUTB source current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .0.5 A
OUTA/OUTB sink current (peak) . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. .. .  1.0 A
Analog inputs (FB, CS) . . . . . . . . . . . . . . . . . .  . 0.3 V to VDD+0.3 V, not to exceed 6 V
Power dissipation at T_A = 25 (N Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .  1 W
Power dissipation at T_A = 25 (D Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Power dissipation at T_A = 25 (PW Package) . . . . . . . . . . . . . . . . . . . . .. . . . . . 400 mW
Storage temperature, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65 to 150
Junction temperature, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 to 150
Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300


Description

The UCC3808 is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC3808 contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching power supplies with minimal external parts count.

The UCC3808 dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to 200 ns depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. (continued)