PowerPC 604e ™

This section summarizes features of the 604e's implementation of the PowerPC architecture.
Major features of the 604e are as follows:
• High-performance, superscalar microprocessor
- As many as four instructions can be issued per clock
- As many as seven instructions can start executing per clock (including three integer instructions)
- Single-clock-cycle execution for most instructions
• Seven independent execution units and two register files
- BPU featuring dynamic branch prediction
Two-entry reservation station
Out-of-order execution through two branches
Shares dispatch bus with CRU
64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can be disabled and invalidated.
512-entry branch history table (BHT) with two bits per entry for four levels of prediction-not-taken, strongly not-taken, taken, strongly taken
- Condition register logical unit
Two-entry reservation station
Shares dispatch bus with BPU
- Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
Instructions that execute in the SCIU take one cycle to execute; most instructions that execute in the MCIU take multiple cycles to execute.
Each SCIU has a two-entry reservation station to minimize stalls
The MCIU has a single-entry reservation station and provides early exit (three cycles) for 16- x 32-bit and overflow operations.
Thirty-two GPRs for integer operands
- Three-stage floating-point unit (FPU)
Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
Supports non-IEEE mode for time-critical operations
Fully pipelined, single-pass double-precision design
Hardware support for denormalized numbers
Two-entry reservation station to minimize stalls
Thirty-two 64-bit FPRs for single- or double-precision operands
- Load/store unit (LSU)
Two-entry reservation station to minimize stalls
Single-cycle, pipelined cache access
Dedicated adder performs effective address (EA) calculations
Performs alignment and precision conversion for floating-point data
Performs alignment and sign extension for integer data
Four-entry finish load queue (FLQ) provides load miss buffering
Six-entry store queue
Supports both big- and little-endian modes
• Rename buffers
- Twelve GPR rename buffers
- Eight FPR rename buffers
- Eight condition register (CR) rename buffers
• Completion unit
- The completion unit retires an instruction from the 16-entry reorder buffer when all instructions ahead of it have been completed and the instruction has finished execution.
- Guarantees sequential programming model (precise exception model)
- Monitors all dispatched instructions and retires them in order
- Tracks unresolved branches and flushes executed, dispatched, and fetched instructions if branch is mispredicted
- Retires as many as four instructions per clock
• Separate on-chip instruction and data caches (Harvard architecture)
- 32-Kbyte, four-way set-associative instruction and data caches
- LRU replacement algorithm
- 32-byte (eight-word) cache block size
- Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical address space as real address space.)
- Cache write-back or write-through operation programmable on a per page or per block basis
- Instruction cache can provide four instructions per clock; data cache can provide two words per clock
- Caches can be disabled in software
- Caches can be locked
- Parity checking performed on both caches
- Data cache coherency (MESI) maintained in hardware
- Secondary data cache support provided
- Instruction cache coherency maintained in hardware
- Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache block was made available to the requesting unit at the time it was burst into the line-fill buffer. Subsequent data was unavailable until the cache block was filled. On the 604e, subsequent data is also made available as it arrives in the line-fill buffer.
• Separate memory management units (MMUs) for instructions and data
- Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size
- Both TLBs are 128-entry and two-way set associative
- TLBs are hardware reloadable (that is, the page table search is performed in hardware)
- Separate IBATs and DBATs (four each) also defined as SPRs
- Separate instruction and data translation lookaside buffers (TLBs)
- LRU replacement algorithm
- 52-bit virtual address; 32-bit physical address
• Bus interface features include the following:
- Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, 5:1, 11:2, 6:1, 13:2, and 7:1)
- A 64-bit split-transaction external data bus with burst transfers
- Support for address pipelining and limited out-of-order bus transactions
- Four burst write queues-three for cache copyback operations and one for snoop push operations
- Two single-beat write queues
- Additional signals and signal redefinition for direct-store operations
- Provides a data streaming mode that allows consecutive burst read data transfers to occur without intervening dead cycles. This mode also disables data retry operations.
-No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows read operations. This improves performance on read operations for systems that do not use the DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock cycle sooner than if normal mode is used.
• Multiprocessing support features include the following:
- Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are provided in the instruction cache to indicate only whether a cache block is valid or invalid.
- Separate port into data cache tags for bus snooping
- Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations
• Power management
- NAP mode supports full shut down and snooping
- Operating voltage of 1.9 ±100 mV
• Performance monitor can be used to help in debugging system designs and improving software efficiency, especially in multiprocessor systems.
• In-system testability and debugging features through JTAG boundary-scan capability

Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: Power up/down sequence must be adhered to to avoid device damage.
• The power-up sequence is GND, Vdd, OVdd
• The power-down sequence is OVdd, Vdd, GND In either case the rule OVdd Vdd 2.0V must be followed.
3. Caution: During system power-up, any 604e signal VDDcore must not exceed 2.0V
4. Caution: 604e inputs are not 5V tolerant.

The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. The 604e implements the PowerPC architecture as it is specified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing, and related features.

The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven instructions can finish execution in parallel. The 604e has seven execution units that can operate in parallel-a floating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a load/store unit (LSU), and three integer units (IUs)-two single-cycle integer units (SCIUs) and one multiple-cycle integer unit (MCIU).

This parallel design, combined with the PowerPC architecture's specification of uniform instructions that allows for rapid execution times, yields high efficiency and throughput. The 604e's rename buffers, reservation stations, dynamic branch prediction, and completion unit increase instruction throughput, guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture specification refers to all exceptions as interrupts.)The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and the cache use least-recently used (LRU) replacement algorithms.

The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple masters to compete for system resources through a central external arbiter.

Additionally, on-chip snooping logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and burst data transfers for memory accesses and memory-mapped I/O accesses.

The 604e uses an advanced, 1.9V CMOS process technology and is fully compatible with 3.3V TTL devices.