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MC74HC174A

Features: • Output Drive Capability: 10 LSTTL Loads• TTL NMOS Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 mA• In Compliance with the Requirements Defined by JEDEC Stand...

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SeekIC No. : 004416908 Detail

MC74HC174A: Features: • Output Drive Capability: 10 LSTTL Loads• TTL NMOS Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 ...

MC74HC174A Data Sheet

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Part Number:
MC74HC174A
Supply Ability:
5000

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Product Details

Description



Features:

• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
vcc DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
VOUT DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
LIN DC Input Current, per Pin ±20 mA
IOUT DC Onput Current, per Pin ±25 mA
ICC DC Supply Current Per Supply Pin ±50 mA
PD Power dissipation in still air piastic DIP
SOIC package
750
500		 mW
TSTG Storage Temperature 65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260 °C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
?Derating - Plastic DIP: 10 mW/ from 65to 125
Ceramic DIP: 10 mW/ from 100 to 125
SOIC Package: 7 mW/ from 65 to 125
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).


Description

The MC74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of six D flipflops with common Clock and Reset inputs. Each flipflop is loaded with a lowtohigh transition of the Clock input. Reset is asynchronous and activelow.




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