M24C02

These I2 C-compatible electrically erasable pro- grammable memory (EEPROM) devices M24C02 are orga-nized as 2048/1024/512/256/128x8 (M24C16,M24C08, M24C04, M24C02, M24C01).

I2C uses a two wire serial interface M24C02, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code(1010) in accordance with the I2C bus definition.

The M24C02 behaves as a slave in the I2C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat- ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device Select Code and RW  bit (as described in Table 2.),terminated by an acknowledge bit.

When writing data to the memory, the M24C02 in-serts an acknowledge bit during the 9th bit time,following the bus master's 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.