IN74ACT193

Features: • TTL/NMOS Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 A; 0.1 A @ 25• Outputs Source/Sink 24 mAPinoutSpecifications Characteristics Symbol Rating Unit Su...

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IN74ACT193 Picture
SeekIC No. : 004374884 Detail

IN74ACT193: Features: • TTL/NMOS Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 A; 0.1 A @ 25&#...

floor Price/Ceiling Price

Part Number:
IN74ACT193
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/2/15

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Product Details

Description



Features:

• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 A; 0.1 A @ 25
• Outputs Source/Sink 24 mA



Pinout

  Connection Diagram


Specifications

Characteristics Symbol Rating Unit
Supply voltage range

DC input voltage

DC output voltage
VCC

VIN

VOUT
-0.5 to +20

-0.5~VCC + 0.5

-0.5~VCC + 0.5
V

V

V
Input diode current

DC Output Sink/Source Current, per Pin
IIN

IOUT
±20

±50
mA
Power Dissipation in Still Air, Plastic DIP+ SOIC Package+

DC Supply Current, VCC and GND Pins
PD

I CC

750
500

±50

mW

mA
DC output current TSTG -65 to 150
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) TL 260

*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65° to 125
SOIC Package: : - 7 mW/ from 65° to 125




Description

The IN74ACT193 is identical in pinout to the LS/ALS192, HC/HCT192. The IN74ACT193 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

The counter of the IN74ACT193 has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TCD) and Terminal Count Up (TCU) Outputs are provided to enable cascading of both up and down counting functions. The TCD output of the IN74ACT193  produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TCU and TCD outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device.




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