ICS9248-92

The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements.

Supply Voltage ................................................ 5.5 V
Logic Inputs .................. GND 0.5 V to  V_DD +0.5 V
Ambient Operating Temperature ............0 to +70
Case Temperature ..........................................  115
Storage Temperature.......................65 to +150

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Features include two strong CPU, seven PCI and eight SDRAM clocks. 
Three reference outputs of the ICS9248-92 are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output (ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs).

PWR_DWN# pin of the ICS9248-92 allows low power mode by stopping crystal OSC and PLL stages. For optional power  management, CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will stop PCICLK (0:5) clocks

PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.

The ICS9248-92 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.