HS-81C56RH

The HS-81C55RH/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened Self- Aligned Junction Isolated (SAJI) silicon gate technology.

Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices.

The HS-81C55RH/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system.

The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply.

Specifications for Rad Hard QML devices HS-81C56RH are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are contained in SMD 5962-96766. A HS-81C56RH "hot-link" is provided
on our homepage for downloading.