DM74S163

Supply Voltage . . . . . . . . .  . . . . .  . . . . .  . . . . .  . .  . . . . . . . .  . . . . .  . 7V
Input Voltage  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . .  . . . . . 5.5V
Operating Free Air Temperature Range . . . . .  . . . . .  .  . .  0°C to +70°C
Storage Temperature Range  . . . . .  . . . . .  . . . . .  . . . −65°C to +150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.

These DM74S163 synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output of DM74S163  counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform.

These DM74S163 counters are fully programmable; that is, the outputs of DM74S163 may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be HIGH to count, and
input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-leveloutput pulse with a duration approximately equal to the HIGH-level portion of the Q_A output. This HIGH-level overflow ripple carry pulse can be used to enable successive
cascaded stages.