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CY7C1041AV33

Features: •Fast access times: 10, 12 ns•Fast OE</a>access times: 5, 6, and 7 ns•Single +3.3V ±0.3V power supply•Fully static-no clock or timing strobes necessary•All inputs and outputs are TTL-compatible•Three state outputs•Center power and ground pi...

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SeekIC No. : 004319783 Detail

CY7C1041AV33: Features: •Fast access times: 10, 12 ns•Fast OE</a>access times: 5, 6, and 7 ns•Single +3.3V ±0.3V power supply•Fully static-no clock or timing strobes necessary•...

CY7C1041AV33 Data Sheet

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Part Number:
CY7C1041AV33
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•Fast access times: 10, 12 ns
•Fast OE</a> access times: 5, 6, and 7 ns
•Single +3.3V ±0.3V power supply
•Fully static-no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•Center power and ground pins for greater noise immunity
•Easy memory expansion with CE</a> and OE</a> options
•Automatic CE</a> power-down
•High-performance, low power consumption, CMOS double-poly, double-metal process
•Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil TSOP


Pinout

Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guide-lines, not tested.)
Voltage on VCC Supply Relative to VSS.........0.5V to +4.6V
VIN .........................................................0.5V to VCC+0.5V
Storage Temperature (plastic).....................55°C to +125°
Junction Temperature ..................................................+125°
Power Dissipation .........................................................1.0W
Short Circuit Output Current .......................................50 mA


Description

The CY7C1049AV33\GVT73512A8 is organized as a 262,144x 16 SRAM using a four-transistor memory cell with a high-per-formance, silicon gate, low-power CMOS process. Cypress SRAMs are fabricated using double-layer polysilicon, dou-ble-layer metal technology.

CY7C1041AV33 offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased sys-tem flexibility and eliminating bus contention problems, CY7C1041AV33 offers Chip Enable (CE</a>), separate Byte Enable controls (BLE</a> and BHE) and Output Enable (OE</a>) with this organization.

CY7C1041AV33 offers a low-power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.




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