CD74HCT563

• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 13ns at V_CC = 5V,
C_L = 15pF, T_A = 25^oC (Data to Output)
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1mA at V_OL, V_OH

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . .. -0.5V to 7V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I_O
For -0.5V < V_O < V_CC + 0.5V. . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . .±25mA
DC V_CC or Ground Current, I_CC . . . . . . . . . . . .  . .±50mA
Operating Conditions
Temperature Range, T_A . . . . . . . . . . . . .. -55^oC to 125^oC
Supply Voltage Range, V_CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V_I, V_O . . . . . . . . . 0V to V_CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) _JA (^oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature . . . . . . . . . . .  . . 150^oC
Maximum Storage Temperature Range . .-65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . 300^oC
(SOIC - Lead Tips Only)


CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. _JA is measured with the component mounted on an evaluation PC board in free air.

The Harris CD74HC533, CD74HCT533, CD74HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.

CD74HCT563 outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (OE) controls the threestate outputs. When the output enable (OE) is high the outputs are in the high impedance state. The latch operation is independent to the state of the output enable.

The CD74HC533 and CD74HCT533 are identical in function to the CD74HC563 and CD74HCT563 but have different pinouts. The CD74HC533 and CD74HCT533 are similar to the CD74HC373 and CD74HCT373; the latter are noninverting types.