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CD74HC109

Features: • Asynchronous Set and Reset• Schmitt Trigger Clock Inputs• Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,TA = 25oC• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL...

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SeekIC No. : 004311964 Detail

CD74HC109: Features: • Asynchronous Set and Reset• Schmitt Trigger Clock Inputs• Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,TA = 25oC• Fanout (Over Temperature Range)- Standard Outputs...

CD74HC109 Data Sheet

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Part Number:
CD74HC109
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

• Asynchronous Set and Reset
• Schmitt Trigger Clock Inputs
• Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA


Description

The 'HC109 and 'HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The CD74HC109 flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high.

However, both set and reset going high simultaneously results in an unpredictable output condition.




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