CD74ACT280

Features: Typical Propagation Delay - 6ns at VCC = 5V, TA = 25, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption• Balanced Pr...

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CD74ACT280 Picture
SeekIC No. : 004311917 Detail

CD74ACT280: Features: Typical Propagation Delay - 6ns at VCC = 5V, TA = 25, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design̶...

floor Price/Ceiling Price

Part Number:
CD74ACT280
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

Typical Propagation Delay
  - 6ns at VCC = 5V, TA = 25, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
  - Fanout to 15 FAST™ ICs
  - Drives 50W Transmission Lines


Pinout

  Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . .  . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .     . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . .  . .±100mA
 


Description

The 'AC280 and 'ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (O output is HIGH)when an even number of data inputs is HIGH. Odd parity is indicated (E output is HIGH) when an odd number of data inputs is HIGH. Parity checking for words larger than nine bits can be accomplished by tying the E output to any input of an additional 'AC280, 'ACT280 parity checker.




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