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74AHCT595

Features: · ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 VCDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger actions· Inputs accept voltages higher than VCC· For AHC only: operates with CMOS input levels· For AHCT...

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SeekIC No. : 004249258 Detail

74AHCT595: Features: · ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 VCDM EIA/JESD22-C101 exceeds 1000 V· Balanced propagation delays· All inputs have Schmitt-trigger acti...

74AHCT595 Data Sheet

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Part Number:
74AHCT595
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
· Balanced propagation delays
· All inputs have Schmitt-trigger actions
· Inputs accept voltages higher than VCC
· For AHC only: operates with CMOS input levels
· For AHCT only: operates with TTL input levels
· Specified from -40 to +85 °C and from-40 to +125 °C.


Application

· Serial-to-parallel data conversion
· Remote control holding register.


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
VCC supply voltage   -0.5 +7.0 V
IIK input clamping current VI < -0.5 V; note 1 - -20 mA
VI input voltage   -0.5 +7.0 V
IOK output clamping current -0.5 > VO > VCC + 0.5 V; note 1 - ±20 mA
IO output current -0.5 < VO < VCC + 0.5 V - ±25 mA
ICC supply current   - ±75 mA
Tstg storage temperature   -65 +150
PD power dissipation per package for temperature range: -40 to +125 °C; note 2 - 500 mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.


Description

The 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register has separate clocks.

Data of the 74AHCT595 is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.

The shift register of the 74AHCT595 has a serial input (DS) and a serial standard output (Q7') for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.




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