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74AHCT574

Features: · Balanced propagation delays· All inputs have a Schmitt-trigger action· 3-state non-inverting outputs for bus orientated applications· 8-bit positive, edge-triggered register· Independent register and 3-state buffer operation· Common 3-state output enable input· For 74AHC574 only: opera...

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SeekIC No. : 004249256 Detail

74AHCT574: Features: · Balanced propagation delays· All inputs have a Schmitt-trigger action· 3-state non-inverting outputs for bus orientated applications· 8-bit positive, edge-triggered register· Independent...

74AHCT574 Data Sheet

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Part Number:
74AHCT574
Supply Ability:
5000

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Product Details

Description



Features:

· Balanced propagation delays
· All inputs have a Schmitt-trigger action
· 3-state non-inverting outputs for bus orientated applications
· 8-bit positive, edge-triggered register
· Independent register and 3-state buffer operation
· Common 3-state output enable input
· For 74AHC574 only: operates with CMOS input levels
· For 74AHCT574 only: operates with TTL input levels
· ESD protection:
·HBM JESD22-A114E exceeds 2000 V
·MM JESD22-A115-A exceeds 200 V
·CDM JESD22-C101C exceeds 1000 V
· Multiple package options
·Specified from -40 °C to +85 °C and from -40 °C to +125 °C


Specifications

Symbol Parameter Conditions Min Max Unit
VCC supply voltage   -0.5 +7.0 V
IIK input clamping
current		 VI < -0.5 V[1] -20   mA
VI input voltage   -0.5 +7.0 V
IOK output clamping
current		 VO < -0.5 V or VO > VCC + 0.5 V[1] - ±20 mA
IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA
ICC quiescent supply
current		   - 75 mA
IGND ground current   -75 - mA
Tstg storage temperature   -65 +150
Ptot total power dissipation Tamb = -40 °C to +125 °C[2]      
  SO20 package [2]   500 mW
  TSSOP20 package [3]   500 mW
  DHVQFN20 package [4] - 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
[3] Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] Ptot derates linearly with 4.5 mW/K above 60 °C.


Description

The 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74AHCT574 are octal D-type flip-flops featuring separate D-type in
puts for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.

The 8 flip-flops of the 74AHCT574 will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.

When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

The 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but has non-inverting outputs. The 74AHCT574 is functionally identical to the 74AHCT374, but has a different pinning.




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