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74ACT377

Features: · ICC reduced by 50%· Ideal for addressable register applications· Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common clock· Outputs source/sink 24 mA· See 273 for master reset version· See 373 for transparent latch ver...

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SeekIC No. : 004249068 Detail

74ACT377: Features: · ICC reduced by 50%· Ideal for addressable register applications· Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common c...

74ACT377 Data Sheet

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Part Number:
74ACT377
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/6/11

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Product Details

Description



Features:

· ICC reduced by 50%
· Ideal for addressable register applications
· Clock enable for address and data synchronization applications
· Eight edge-triggered D-type flip-flops
· Buffered common clock
· Outputs source/sink 24 mA
· See 273 for master reset version
· See 373 for transparent latch version
· See 374 for 3-STATE version
· ACT377 has TTL-compatible inputs


Specifications

Supply Voltage (VCC)                   -0.5V to +7.0V
DC Input Diode Current (IIK)
    VI = -0.5V                                          -20 mA
    VI = VCC + 0.5V                                +20 mA
DC Input Voltage (VI)          -0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
    VO = -0.5V                                        -20 mA
    VO = VCC + 0.5V                              +20 mA
DC Output Voltage (VO)      -0.5V to VCC + 0.5V
DC Output Source
    or Sink Current (IO)                         ±50 mA
DC VCC or Ground Current
    per Output Pin (ICC or IGND)             ±50 mA
Storage Temperature (TSTG)     -65 to -150
Junction Temperature (TJ)
    PDIP                                                    140


Description

The 74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register of the 74ACT377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.




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