74AC11238

• Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
• Noninverting Version of 4AC11138
• Incorporates 3 Enable Inputs to Simplify Cascading and/or Data Reception
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC
(Enhanced-Performance Implanted CMOS) 1-
m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

The 74AC11238 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions of the 74AC11238 at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The 74AC11238 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC11238 is characterized for operation from 40°C to 85°C.