ZPSD5XX

Features:

 Single Supply Voltage:
  5 V±10% for PSD5XX
  2.7 to 5.5 V for PSD5XX-V
 Up to 1 Mbit of UV EPROM
 Up to 16 Kbit SRAM
 Input Latches
 Programmable I/O ports
 Page Logic
 Programmable Security


Specifications

Symbol	Parameter	Condition	Min	Max	Unit
TSTG	Storage Temperature	CLDCC	65	+ 150	°C
		PLDCC	65	+ 125	°C
	Operating Temperature	Commercial	0	+ 70	°C
		Industrial	40	+ 85	°C
		Military	55	+ 125	°C
	Voltage on any Pin	With Respect to GND	0.6	+ 7	V
VPP	Programming Supply Voltage	With Respect to GND	0.6	+ 14	V
VCC	Supply Voltage	With Respect to GND	0.6	+ 7	V
	ESD Protection		>2000		V

Description

The PSD5XX family is a microcontroller peripheral that integrates high-performance and user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The PSD5XX is also loaded with a variety of features, such as Counter/Timers, Interrupt controller, power management, and page logic. The PSD5XX products also provide a powerful microcontroller interface that eliminates the need for external "glue logic". The no "glue logic" concept provides a user-programmable interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that is easy to use. The part's integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller.

The PSD5XX provides three Zero-power PLDs (ZPLDs): a Decode PLD (DPLD), a General-purpose PLD (PLD), and a Peripheral PLD (PPLD). The ZPLDs have a total of 61 inputs, 140 product terms, 30 macrocells, and 24 I/O connections. A configuration bit (Turbo) can be set by the MCU, and will automatically place the ZPLDs into standby if no inputs are changing. The ZPLDs are designed to consume minimum power using Zero Power CMOS technology that uses low standby current. Unused product terms are automatically disabled, also reducing power, regardless of the Turbo bit setting.

The main function of the DPLD PSD5XX is to perform address decoding for the internal I/O ports,EPROM, and SRAM. The address decoding can be based on up to 24 bits of address inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports separate program and data spaces (for 8031 compatible MCUs).

The General-purpose PLD (GPLD)PSD5XX  can be used to implement various logic defined by the user, such as:
• State machines
• Loadable counters and shift registers
• Inter-processor mailbox
• External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 61 inputs, 118 product terms, 24 macrocells, and 24 I/O pins.

The Peripheral PLD (PPLD) PSD5XX generates outputs to the Counter/Timer unit and the Interrupt Controller. The PPLD outputs to the Counter/Timer enable, disable, or trigger counting or time capture. The PPLD outputs to the Interrupt Controller enables the user to define conditions for interrupt generation.

The Counter/Timer unit PSD5XX provides four 16-bit highly flexible Counter/Timers. Each has five modes of operation: pulse, waveform, event counting, time capture, and watchdog (real-time clock). Each Counter/Timer can be programmed to count up or down. The inputs to the Counter/Timer, which enable/disable counting or trigger an operation, can originate from the PPLD directly or directly from the pins. The maximum operating frequency of each counter is 7.5 MHz. The input clock can be divided (by up to 280) before driving the Counter/Timer unit using the 4 to 280 prescaler.

The Interrupt Controller PSD5XX has eight levels of priority encoding. It accepts four user-defined interrupts and four terminal counts from the Counter/Timer. Each interrupt can be individually masked and configured to be level or edge sensitive. A 3-bit interrupt vector is generated that can be read by the microcontroller. The serviced interrupt will be cleared automatically after the microcontroller has read the interrupt vector.

The PSD5XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be individually configured to provide many functions, including the following:
• MCU I/O
• ZPLD I/O
• Latched address output (for MCUs with multiplexed data bus)
• Special function I/O (Counter/Timer and Interrupts)
• Data bus (for MCUs with non-multiplexed data bus).

The PSD5XX can easily interface with virtually any 8- or 16-bit microcontroller with a multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the ZPLDs, enabling the user to generate signals for external devices. The PSD5XX can generate a reset output based on the RESET input (includes hysteresis).

The PSD5XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four equal-sized blocks. Each block can occupy a different address location, allowing for versatile address mapping. The access time of the EPROM includes the address latching and DPLD decoding.

The PSD5XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a power failure. Therefore, you can place data in the optional SRAM that you want to keep after the power is switched off. Power switch-over to the battery automatically occurs when Vcc drops below Vstby.

A four-bit Page Register PSD5XX enables easy access to the I/O section, EPROM, and SRAM for microcontrollers with limited address space. The Page Register outputs are connected to the ZPLDs and thus can also be used for external paging schemes.

The Power Management Unit (PMU) of the PSD5XX enables the user to control the power consumption on selected functional blocks, based on system requirements. For microcontrollers that do not generate a chip select input for the PSD, the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down or Sleep Mode, based on the inactivity of ALE (or AS).

Implementing your design has never been easier than with PSDsoft-WSI's software development suite. Using PSDsoft, you can do the following:
• Configure your PSD5XX to work with virtually any microcontroller
• Specify what you want implemented in the programmable logic using a design file
• Simulate your design
• Download your design to the part using a programmer.