ZL50418

• Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch
• 16 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces
• 2 Gigabit Ports with GMII, PCS and 10/100 interface options per port
• Gigabit port supports hot swap in managed configuration.
• Supports 8/16-bit CPU interface in managed mode
• Serial interface in unmanaged mode
• Supports two Frame Buffer Memory domains with SRAM at 100 MHz
• Supports memory size 2 MB, or 4 MB
• Two SRAM domains (2 MB or 4 MB) are required
• Applies centralized shared memory architecture
• Up to 64 K MAC addresses
• Maximum throughput is 3.6 Gbps non-blocking
• High performance packet forwarding (10.712 M packets per second) at full wire speed
• Provides port based and ID tagged VLAN support (IEEE 802.1Q), up to 255 VLANs
• Supports IP Multicast with IGMP snooping
• Supports spanning tree with CPU, on per port or per VLAN basis
• Packet Filtering and Port Security
• Static address filtering for source and/or destination MAC
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning. Each port may independently use this mode.
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Supports Ethernet multicasting and broadcasting and flooding control
• Supports per-system option to enable flow control for best effort frames even on QoS-enabled ports
• Traffic Classification
• 4 transmission priorities for Fast Ethernet ports with 2 dropping levels
• Classification based on:
- Port based priority
- VLAN Priority field in VLAN tagged frame
- DS/TOS field in IP packet
- UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
• QoS Support
• Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
• 3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group. Or 8 groups for 10/100 ports with up to 2 10/100 ports per group
• Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit trunking group has one more option, based on source port
• Port Mirroring to any two ports of 0-15 in managed mode or to a dedicated mirroring port in unmanaged mode
• Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only (without serial interface)
• Built-in MIB statistics counters
• Recognizes Simple Bandwidth Management (SBM) and Resource Reservation Potocol (RSVP) packets and forwards to CPU
• Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
• Built-in reset logic triggered by system malfunction
• Built-in self test for internal and external SRAM
• I2C EEPROM for configuration
• 553 BGA package

Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied.

The ZL50418 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch applications. The Gigabit ports can also support 10/100 M.

The ZL50418 supports up to 64 K MAC addresses and up to 255 port-based Virtual LANs (VLANs). The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate  andwidth of 12.8 Gbps to support full wire speed on all ports simultaneously.

With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the ZL50418 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50418 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).

The ZL50418 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and the other two groups to 10/100 ports where each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.

In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50418 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports.

The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to SERDES chips. The PCS can be bypassed to provide a GMII interface.

Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers of ZL50418 is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution.

The ZL50418 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50418 is packaged in a 553-pin Ball Grid Array package.