ZL50120

General
• Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across a packet network
• On chip dual reference Stratum 3 DPLL
• Grooming capability for Nx64 Kbps trunking
• Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors
Circuit Emulation Services
• Complies with ITU-T recommendation Y.1413
• Complies with IETF PWE3 draft standards CESoPSN and SAToP
• Complies with CESoP Implementation Agreements from MEF 8 and MFA 8.0.0
• Structured, synchronous CESoP with clock recovery
• Unstructured, asynchronous CESoP with integral per-stream clock recovery
Customer Side TDM Interfaces
• Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
• H.110, H-MVIP, ST-BUS backplane
• Up to 128 bi-directional 64 Kbps channels
• Direct connection to LIUs, framers, backplanes
Customer Side Packet Interfaces
• 100 Mbps MII Fast Ethernet (ZL50118/19/20 only) (may also be used as a second provider side packet interface)
Provider Side Packet Interfaces
• 100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet

* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply  urrent is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.