ZL50114

General
• Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across a packet network
• Grooming capability for Nx64 Kbps trunking
 Circuit Emulation Services
• Complies with ITU-T recommendation Y.1413
• Complies with IETF PWE3 draft standards for CESoPSN and SAToP
• Complies with CESoP draft IAs for MEF and MFA
• Structured, synchronous CESoP with clock recovery
• Unstructured, asynchronous CESoP, with integral per stream clock recovery
TDM Interfaces
• Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation
Network Interfaces
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces
System Interfaces
• Flexible 32 bit host CPU interface (Motorola PowerQUICC™ compatible)
• On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms

* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.

The ZL50110/11/ZL50114 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50110/11/ZL50114 provides both structured and unstructured circuit emulation services over packet (CESoP) for up to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also supports unstructured T3, E3 and STS-1 streams.

The circuit emulation features in the ZL50110/11/ZL50114 family comply with the ITU Recommendation Y.1413, as well as the emerging CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance (MFA).

The ZL50110/11/ZL50114 also complies with the standards currently being developed within the IETF's PWE3 working group, listed below.
• Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop
• Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) - draft-ietfpwe3- cesopsn

The ZL50110/11/ZL50114 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports. The ZL50110/11/ZL50114 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing  the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL50110/11/ZL50114.

The ZL50110/11/ZL50114 incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation.

The ZL50110/11/ZL50114 is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/14 supports a range of different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The ZL50114 also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used to help minimize latency variation in the TDM data.

Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface. Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to maintain timing integrity.

The ZL50110/11/ZL50114 family includes sufficient on-chip memory that external memory is not required in most applications. This reduces system costs and simplifies the design. For applications that do require more memory (e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.

A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This ZL50114 system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC.