Features: • 8,192 channel x 8,192 channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 input streams and 64 output streams• 4,096 channel x 4,096 channel non-blocking Backplane input to...
ZL50051: Features: • 8,192 channel x 8,192 channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 inpu...
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• 8,192 channel x 8,192 channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 input streams and 64 output streams
• 4,096 channel x 4,096 channel non-blocking Backplane input to Local output stream switch
• 4,096 channel x 4,096 channel non-blocking Local input to Backplane output stream switch
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096 channel x 4,096 channel non-blocking Local input to Local output stream switch
• Backplane port accepts 32 input and 32 output ST-BUS streams with a fixed data rate of 8.192 Mbps, or 16 input and 16 output ST-BUS streams with a fixed data rate of 16.384 Mbps
• Local port accepts 32 input and 32 output STBUS streams with a fixed data rate of 8.192 Mbps, or 16 input and 16 output ST-BUS streams with a fixed data rate of 16.384 Mbps
• Exceptional input clock jitter tolerance (17 ns)
• Per-stream bit delay for Local and Backplane input streams
• Per-stream advancement for Local and Backplane output streams
• Constant 2-frame throughput delay for frame integrity
• Per-channel high impedance output control for Local and Backplane streams
• Per-channel driven-high output control for Local and Backplane streams
• Per-channel message mode for Local and Backplane output streams
• Connection memory block programming for fast device initialization
• Automatic selection between ST-BUS and GCI-Bus operation
• Non-multiplexed Motorola microprocessor interface
• Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
• Memory Built-In-Self-Test (BIST), controlled via microprocessor register
• 1.8 V core supply voltage
• 3.3 V I/O supply voltage
• 5 V tolerant inputs, outputs and I/Os
Parameter | Symbol | Min | Max | Units | |
1 | Core Supply Voltage | V DD_CORE | -0.5 | 2.5 | V |
2 | I/O Supply Voltage | V DD_IO | -0.5 | 5.0 | V |
3 | PLL Supply Voltage | V DD_PLL | -0.5 | 2.5 | V |
4 | 4 Input Voltage (non-5 V tolerant inputs) | V I | -0.5 | V DD_IO+0.5 | V |
5 | Input Voltage (5 V tolerant inputs) | V I_5V | -0.5 | 7.0 | V |
6 | Continuous Current at digital outputs | Io | 15 | mA | |
7 | Package power dissipation | PD | 1.5 | W | |
8 | Storage temperature | TS | - 55 | +125 |