ZL38004

• 100 MHz (200 MIPs) Zarlink voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller
• On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM
• Dual ADCs with input buffer gain selection programmable to either 8 or 16 kHz sampling
• Dual DACs with output sampling of 8, 16, 44.1 and 48 kHz and internal output driver
• 2048 tap Filter co-processor shared across up to 16 separate functions in 128 tap increments
• Dual function Inter-IC Sound (I²S) or Secondary TDM port
• Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
• Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25 MHz
• Watchdog and 2 auxiliary timers
• 11 General Purpose Input/Output (GPIO) pins
• General purpose UART port
• Bootloadable for future Zarlink software upgrades
• External oscillator or crystal/ceramic resonator
• 1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
• IEEE-1149.1 compatible JTAG port

The ZL38004 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction) firmware applications available from Zarlink Semiconductor. These applications are resident in external memory and are down-loaded by the ZL38004 resident boot code during initialization.

The firmware products and manuals available at the release of this data sheet are: ZLS38500: Acoustic Echo Canceller with Noise Reduction for Hands-Free Car Kits; ZLS38501 Speakerphone. If ZL38004 do not meet your requirements, please contract your local Zarlink Sales Office for the latest firmware releases.

The ZL38004 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Zarlink's Voice Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following:
• Two independent CODECs
• Two PCM ports - ST BUS, GCI, McBSP or SSI operation
• An I²S interface port
• A 2048 tap Filter Co-processor
• Two Auxiliary Timers and a Watchdog Timer
• 11 GPIO pins
• A UART interface
• A Slave SPI port and a Master SPI port
• A timing block that supports master and slave operation
• An IEEE - 1149.1 compatible JTAG port
The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit audio channel. These audio channels may originate and terminate with the CODECs, or be communicated to and from the DSP Core through the PCM ports or the I²S port.