Z89462

Features: ` 100-Pin QFP and 124-Pin PGA Packages` 0to +70 Temperature Range` 3.3- to 5.0-Volt Operating Range40 MHz Operation @ 5.0V 20 MHz Operation @ 3.3V` Six RAM Pointers for 4K-Word RAM Banks` Three Maskable Vectored Interrupts, Edge or Level Trigger Selectable` Enhanced Instruction Set` Sing...

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Z89462 Picture
SeekIC No. : 004550444 Detail

Z89462: Features: ` 100-Pin QFP and 124-Pin PGA Packages` 0to +70 Temperature Range` 3.3- to 5.0-Volt Operating Range40 MHz Operation @ 5.0V 20 MHz Operation @ 3.3V` Six RAM Pointers for 4K-Word RAM Banks` ...

floor Price/Ceiling Price

Part Number:
Z89462
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

` 100-Pin QFP and 124-Pin PGA Packages
` 0to +70 Temperature Range
` 3.3- to 5.0-Volt Operating Range
          40 MHz Operation @ 5.0V
          20 MHz Operation @ 3.3V
` Six RAM Pointers for 4K-Word RAM Banks
` Three Maskable Vectored Interrupts, Edge or Level Trigger Selectable
` Enhanced Instruction Set
` Single-Cycle Instruction Execution
` Four-Stage Pipeline
` Dual 8/16-Bit CODEC Interface
` Wait-State Generator
` Two 16-Bit Timer/Counters
` Dynamic Program Bus Sizing



Pinout

  Connection Diagram





  Connection Diagram


Specifications

+70°
Description Min Max Units
Voltages on VDD with Respect to VSS 0.5 +5.5V
Voltages on All Pins with Respect to VSS 0.5 (VDD+0.5) V
TSTG Storage Temp 85° +150°
TA Oper Ambient Temp +70°



Description

The Z89462 is a high-performance Digital Signal Processor (DSP) optimized for processing and transferring data. This enhanced processor provides an upward migration path for its Z89C00/Z89321 predecessors.

The DSP provides three 12-bit Register Pointers for each RAM bank. These pointers may be incremented or decremented automatically to implement circular buffers without software overhead.

Three prioritized and individually maskable interrupts are provided for use by external peripherals requiring service from the DSP. The interrupt inputs can be individually conditioned for edge or level trigger. Acknowledgement of an activated interrupt occurs at the end of an instruction execution.

Two banks of 512 x 16-bit data RAM are available. Expansion of the on-chip data RAM is provided through future upgrades.

External interfaces include Address Bus and Data Bus for external Program Memory, Address Bus and Data Bus for external Data Memory, three vectored interrupt ports, and two input/two output user ports.




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