Z84C01

The Z84C01 is an 8-bit microprocessor (hereinafter referred to as MPU) with a built-in clock generator/controlter, which provides low power operation and high performance.Built into the Z84C01 is a control function and clock generator for the standby function in addition to: six paired general purpose registers, accumulator, flag registers, an arithmetic-and-logic unit, bus control, memory control and timing control circuits.

Features of the Z84C01 are:(1)commands compatible with the zilog z80 mpu; (2)an auxiliary register provided to each of general purpose registers.; (3)2 index registers 10 addressing modes; (4)built-in refresh circuit for dynamic memory; (5)on-chip clock generator.The Z84C01 is fabricated with Zilog CMOS technology and molded in a 44-pin PLCC or QFP packages.Further, in the following text and explanations for charts and tables, hexadecimal numbers are directly used without giving an identification to explanation of address, etc. so as not to cause confusions.

The absolute maximum ratings of the Z84C01 can be summarized as:(1)voltage on Vcc with respect to Vss:-0.3V to+7V; (2)voltages on all inputs with respect to Vss:-0.3V to Vcc+ 0.3V; (3)operating ambient temperature:see ordering information; (4)storage temperature:-65 to +150.Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.The basic clock period is referred to as a Time or Cycle,and three or more T cycles make up a machine cycle (M1,M2 or M3 for instance). Machine cydes can be extended either by the CIPU automatically inserting one or more Wait states or by the insertion of one or more Wait states by the user.MPU executes one NOP instruction after the internal system clock is restarted and at the same time, sampling an interrupt signal at the rise of T4 state during the execution of this NOP instruction. If the interrupt signal is accepted, MPU executes the interrupt process operation from next cycle.