Features: · Static CMOS Design with Low-Power Standby Mode Option
· 32-Bit Internal Data Paths and ALU
· Operating Frequency
- DC-to-18 MHz at 5V
- DC-to-10 MHz at 3.3V
· Enhanced Instruction Set that Maintains Object-Code Compatibility with Z80® and Z180™ Microprocessors
·16-Bit (64K) or 32-Bit (4G) Linear Address Space
· 16-Bit Data Bus with Dynamic Sizing PRODUCT SPECIFICATION
· Two-Clock Cycle Instruction Execution Minimum
· Four Banks of On-Chip Register Files
· Enhanced Interrupt Capabilities, Including 16-Bit Vector
· Undefined Opcode Trap for Z380™ Instruction Set
· On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
· 100-Pin QFP PackagePinout
SpecificationsVoltage on VDD with respect to VSS ......... 0.3V to +7.0V
Voltage on all pins,
with respect to VSS ....................... 0.3V to (VDD + 0.3)V
Operating Ambient Temperature: .................... 0 to +70
Storage Temperature: ........................... 55 to +150
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DescriptionThe Z380™ Microprocessor is an integrated highperformance microprocessor with fast and efficient throughput and increased memory addressing capabilities. The Z380™ offers a continuing growth path for present Z80-or Z180-based designs, while maintaining Z80® CPU and Z180® MPU object-code compatibility. The Z380™ MPU enhancements include an improved 280 CPU, expanded 4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380 MPU. The basic addressing modes of the Z80 microprocessor have been augmented as follows: Stack Pointer Relative loads and stores, 16-bit and 24-bit indexed offsets, and more flexible Indirect Register addressing, with all of the addressing modes allowing access to the entire 32-bit address space. Additions made to the instruction set, include a full complement of 16-bit arithmetic and logical operations, 16-bit I/O operations, multiply and divide, plus a complete set of register-to-register loads and exchanges.
The expanded basic register file of the Z80 MPU microprocessor includes alternate register versions of the IX and IY registers. There are four sets of this basic Z80 microprocessor register file present in the Z380 MPU, along with the necessary resources to manage switching between the different register sets. All of the register-pairs and index registers in the basic Z80 microprocessor register file are expanded to 32 bits.
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180 address space to a full 4 Gbyte (32-bit) address space. This address space is linear and completely accessible to the user program. The I/O address space is similarly expanded to a full 4 Gbyte (32-bit) range and 16-bit I/O, and both simple and block move are added.
Some features that have traditionally been handled by external peripheral devices have been incorporated in the design of the Z380 microprocessor. The on-chip peripherals reduce system chip count and reduce interconnection on the external bus. The Z380 MPU contains a refresh controller for DRAMs that employs a /CAS-before-/RAS refresh cycle at a programmable rate and burst size.
Six programmable memory-chip selects are available, along with programmable wait-state generators for each chip-select address range.
The Z380 MPU provides flexible bus interface timing, with separate control signals and timing for memory and I/O. The memory bus control signals provide timing references suitable for direct interface to DRAM, static RAM, EPROM, or ROM. Full control of the memory bus timing is possible because the /WAIT signal is sampled three times during a memory transaction, allowing complete user control of edge-to-edge timing between the reference signals provided by the Z380 MPU. The I/O bus control signals allow direct interface to members of the Z80 family of peripherals, the Z8000 family of peripherals, or the Z8500 series of peripherals. Figure 1 shows the Z380 block diagram; Figure 2 shows the pin assignments.
Z380 Data Sheet
