Pinout
SpecificationsSYM Description Min Max Unit
VCC Supply Voltage -0.3 +70 V
TSTG Storage Temp 65° +150° C
TA Operating 0 +70 C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DescriptionThe Z16C32 IUSC (Integrated Universal Serial Controller) is a single- channel multple protocol data communications device with on-chip dual-channel DMA. The integration of a highspeed serial communications channel with a high performance DMA facilitates higher data throughput than is possible with discrete serial/DMA chip combinations. The buffer chaining capabilities combined with features like character counters, frame status block and buffer termination at the end of the frame facilitate sophisticated buffer management that can significantly reduce CPU overhead.
The Z16C32 IUSC is software configurable to satisfy a wide variety of serial communications applications. Offered at 20 Mbit/sec, its fast data transfer rate and multiple protoco l support make it ideal for applications in todays dynamic environment of changing specifications and ever increasing speed. The many programmable features allow the user to tune the device response to meet system requirements and adapt to future changes with software instead of redesigning hardware.
The Z16C32 on-chip DMA channels allow high-speed data transfers for both the receiver and the transmitter. The device supports automatic status transfer through DMA and allows device initialization under DMA control. Each DMA channel can transfer data words in as little as three 50 ns clock cycles and can generate addresses compatible with 32-, 24- or 16-bit memory ranges. The DMA channels may operate in any of four modes: single buffer, pipelined, array- chained, or linked-list. The array-chained and linkedlist modes reduce the problems with segmentation and reassembly of messages in systems. To prevent the DMA from holding bus mastership too long, mastership time may be limited by counting the absolute number of clock cycles, the number of bus transactions, or both.
The Z16C32 CPU bus interface is designed for use with any conventional multiplexed or non-multiplexed bus. The device contains a variety of sophisticated internal functions including two baud rate generators, a digital phase-locked loop,
character counters, and 32-byte FIFOs for both the receiver and transmitter.
The Z16C32 IUSC handles asynchronous formats, synchronous byte-oriented formats (e.g., BISYNC), and synchronous bit-oriented formats such as HDLC. This device supports virtually any serial data transfer application.
The Z16C32 IUSC can generate, and check CRC in any synchronous mode and is programmed to check data integrity in various modes. Access to the CRC value allows system software to resend or manipulate it as needed in various applications.
The Z16C32 IUSC also has facilities for modem controls. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O.
Z16C32 Interrupts are supported by a daisy-chain hierarchy within the serial channel and between the serial channel and the DMA.
Support tools are available to aid the designer in efficiently programming the IUSC. The Technical Manual describes in detail all features presented in this Product Specification and gives programming sequence hints. The EPM™ manual (Electronic Programmers Manual) is an MS-DOS, diskbased programming initialization tool, used in conjunction with the Technical Manual. Also, there are assorted application notes and development boards to assist the designer in hardware/software development.
Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Z16C32 Data Sheet
