XRT94L43

Features:

• Provides DS3/ E3 mapping/de-mapping for up to 12 tributaries through SONET STS-1 or SDH AU-3 and/or TUG-3/AU-4 containers.
• Generates and terminates SONET/SDH section, line and path layers.
• Integrated SERDES with Clock Recovery Circuit.
• Provides SONET frame scrambling and descrambling.
• Integrated Clock Synthesizer that generates 622.08 MHz and 77.76 MHz clock from an external 12.96/ 19.44/77.76 MHz reference clock.
• Provides STS-1 (EC1) mapping/de-mapping for up to 12 STS-1s.
• Integrated 12 E3/DS3/STS-1 De-Synchronizer circuit that de-jitter gapped clock to meet 0.05UIpp jitter requirements.
• Access to Line or Section DCC
• Level 2 Performance Monitoring for E3 and DS3.
• Supports mixing of STS-1E and DS3 or E3 and DS3 tributaries.
• Performs STS-3/STM-1 to STS-12/STM-4 Mapping/ De-Mapping.
• E3 and DS3 framers for both Transmit and Receive directions.
• Complete Transport/Section Overhead Processing and generation per Telcordia and ITU standards.
• Complete Path Overhead processing and generation for one STS-12 or for 12 STS-1s
• Full line APS support for redundancy applications.
• Loopback support for both SONET/SDH as well as E3/DS3/STS-1.
• Boundary scan capability with JTAG IEEE 1149.1
• 8-bit microprocessor interface
• Power Supply 2.5 V for Core and 3.3 V for I/O
• -40°C to +85°C Operating Temperature Range
• Available in a 516 Ball PBGA package

Application

• Network switches
• Add/Drop Multiplexer
• W-DCS Digital Cross Connect Systems




Specifications

Specifications
DataRate(s)	1xOC-12, 4xOC-3, 12xDS3/E3/STS-1
Protocols	n/a
Bus I/F	8-Bit, 77.76MHz
SystemBus I/F	n/a
Pwr Sup	2.5V
Pkgs	PBGA-516

Description



First in a series of pioneering SONET aggregation devices, the XRT94L43 is a framer/mapper/jitter attenuator capable of aggregating 12 DS3/E3/STS-1 data into SONET/SDH STS-12/STM-4. The device offers several new industry functions that distinguish the XRT94L43 in a crowded marketplace. Characteristics including Level 2 performance monitoring, internal clock generation, and simultaneous support for different data rates in the same device illustrate how this product is different than competitive offerings. The XRT94L43 is focused on the growing access and metro area network equipment manufacturers that need to groom or aggregate lower power signals to OC-12.

The XRT93L43 supports the mapping and demapping of 12 channels of T3, E3, or STS-1 rate signals to and from STS-12/STM-4. It has a fully synthesized clocking approach that generates all clock speeds (622 MHz, 77.6 MHz, 19.44 MHz) from a single 6.48, 12.96, 19.44, or 77.76MHz clock signal. This eliminates the need for Telecom Bus/Serial Port Interfaces and additional clocks for jitter attenuator de-synchronization at DS3, E3, and STS-1 data rates, offering designers reduced costs, and more development flexibility. The XRT94L43 can also multiplex and groom four channels of STS-3/STM-1 onto a single STS-12/STM-4 signal. The STS-12 input can be configured either as a 622MHz serial interface or as a 77.76MHz Telecom Bus interface. Both interfaces support 1:1 and 1+1 automatic protection switching.

Desynchronization from the SONET frame to DS3/E3 is provided through 12 independent jitter attenuators. The XRT94L43 jitter attenuators have clock smoothing capability to achieve compliance with Bellcore and ITU-T standards. Customers can expect low jitter DS3 or E3 signals from their line-card designs. The DS3/E3 framers support all common framing formats including C-bit parity, M13, ITU-T G.751 and ITU-T G.832. Outputs are also provided in the form of an STS-1 frame which offers overhead termination and generation capabilities. Pseudo Random Bit sequence generation and detection is included for Bit Error Rate Testing.

The XRT94L43 supports a byte-wide interface through the telecom bus standard for both the STS-12/STM-4 data path as well as the STS-3/STM-1 data paths. In addition, the XRT94L43 handles the generation and termination of the payload overhead. It includes generating transmit payload pointers (H1/H2 bytes) with NDF insertion, and computing and inserting BIP-8 (B1/B2 bytes).

The XRT94L43 is implemented in 0.25 u CMOS and runs from a 2.5V supply. All inputs are CMOS except the serial bus/STS-12 telecom bus, which is PECL for high-speed interfacing. I/O supports 3.3V operation and the device comes in a 516-ball PBGA package that functions over industrial temperature ranges (-40 to 85+ C).