Description
The addition of the XRT94L33 to Exar's pioneering SONET/SDH aggregation device family offers customers a new level of product support for their broadband applications. Capable of aggregating 3 DS3/E3/STS-1 into OC-3/STM-1, the device provides a vital link in Exar's product portfolio spanning T/E to SONET. The XRT94L33 supports Packet Over SONET (POS) and Asynchronous Transfer Mode (ATM) over SONET.
Desynchronization
The process of mapping and subsequent de-mapping of individual DS3 or E3 signals into SONET's Synchronous Payload Envelope (SPE) can introduce excessive jitter and timing irregularities. XRT94L33 Exar's solution uses only one highly integrated programmable PLL so each channel can support multi-rate (DS3, E3 or STS-1) operations. Here jitter/timing irregularities are removed, and then desynchronized to provide a smooth GR-253-CORE specification-compliant clock signal. Once this operation is complete the signal is suitable for retransmission and returned to the data stream. Examples of jitter sources include mapping jitter, caused by bit justification, or stuffing, to match the asynchronous bit rate to a synchronous transport signal; and pointer jitter, the outcome of frequency mismatches between two networks that offset the payload and cause pointer movement.
Product Highlights
The XRT94L33 has an integrated clock and data recovery plus a serializer/ deserializer running at 155.52 MHz in order to support STS-3/STM-1 rate data allowing it to interface to an optical module. The chip offers three mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping functions -- one for each STS-1/DS3/E3 framer.
Mapping and demapping in the XRT94L33 can occur in one of three modes. The first mode allows clear channel DS3, E3 or STS-1 to be directly mapped/ demapped to an STS-3 stream. This mode allows direct seamless connection to an EXAR LIU such as the XRT73L03 for termination on the DS3/E3/STS-1 side. The other two modes allow ATM cells or POS packets to be mapped onto the STS-3 directly. These modes provide termination either through a UTOPIA level II bus for ATM or a POS-PHY bus for POS.
Other features of XRT94L33 include an on-chip clock synthesizer that generates 155.52 and 77.76 MHz clocks from a single 12.96, 19.44 or 77.76 MHz master clock providing development flexibility, reduced cost and ease of design. The device supports 1:1 and 1+1 Automatic Protection Switching (APS) through the K1 and K2 bytes allowing the device to be switched from primary to backup at the frame boundary. Level 2 performance monitoring capability is included allowing the analysis of overhead and payload envelope information with minimal data path delay.
Standards Compliance
Compliant to industry standards, the XRT94L33 supports Bellcore GR-253 by mapping and demapping asynchronous DS3 data into a STS-1 signal. In addition, it provides SDH TUG-3/VC-3 mapping or DS3/E3 in conformance with the ITU-T G. 707. Also, the XRT94L33 supports the ITU-T G.751, G.755, ETSI TBR24, GR253-CORE, GR-499-CORE and ANSI T1.105.03b jitter specifications.
XRT94L33 Data Sheet
