Features: · 2.488 / 2.666 Gbps Transceiver· Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, limiting amplifier and clock data recovery (CDR) functions· Host mode serial microprocessor interface simplifies m...
XRT91L81: Features: · 2.488 / 2.666 Gbps Transceiver· Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, limiting ampli...
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Network Controller & Processor ICs 8-Bit TTL 3.3V temp -45 to 85C;UART
· 2.488 / 2.666 Gbps Transceiver
· Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, limiting amplifier and clock data recovery (CDR) functions
· Host mode serial microprocessor interface simplifies monitor and control
· Provides support for dual fiber rings
· Integrated limiting amplifier accepts differential inputs down to 10mVp-p
· Separate reference and VCXO input ports support multiple de-jittering modes
· On-chip phase detector and charge pump for external VCXO based de-jittering PLL
· Targeted for SONET OC-48/SDH STM-16
The XRT91L81 is a fully integrated SONET/SDH transceiver block for applications in SONET OC-48 allowing the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the highspeed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions.
The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter input clock and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section.