SpecificationsSpecificationsNo. ofCH8DataRate(s)T1/E1/J1Clk RecYesSH/LHS/LTemp.RangeIndOpPwr Sup/Max Cur3.3V +/-5%PkgsfpBGA256, fpBGA329Description The XRT86VX38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Reconfigurable, ...
XRT86VX38: SpecificationsSpecificationsNo. ofCH8DataRate(s)T1/E1/J1Clk RecYesSH/LHS/LTemp.RangeIndOpPwr Sup/Max Cur3.3V +/-5%PkgsfpBGA256, fpBGA329Description The XRT86VX38 is an eight-channel 1.544 Mbit/s or...
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Clock Synthesizer / Jitter Cleaner 3.3V-5V 0.05UI temp -45 to 85C
Specifications | |
No. ofCH | 8 |
DataRate(s) | T1/E1/J1 |
Clk Rec | Yes |
SH/LH | S/L |
Temp.Range | Ind |
OpPwr Sup/Max Cur | 3.3V +/-5% |
Pkgs | fpBGA256, fpBGA329 |
The XRT86VX38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Reconfigurable, Relayless, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VX38 provides protection from power failures and hot swapping.
The XRT86VX38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VX38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921.