XRT86VL32

Features: •Two independent, full duplex DS1 Tx and Rx Framer/LIUs•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation•Supports input PCM and signaling data...

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SeekIC No. : 004549519 Detail

XRT86VL32: Features: •Two independent, full duplex DS1 Tx and Rx Framer/LIUs•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous b...

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Part Number:
XRT86VL32
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

•Two independent, full duplex DS1 Tx and Rx Framer/LIUs
•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation
•Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•Programmable output clocks for Fractional T1/E1/J1
•Supports Channel Associated Signaling (CAS)
•Supports Common Channel Signalling (CCS)
•Supports ISDN Primary Rate Interface (ISDN PRI) signaling
•Extracts and inserts robbed bit signaling (RBS)
•3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1)
•HDLC Controllers Support SS7
•Timeslot assignable HDLC
•V5.1 or V5.2 Interface
•Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission
•Alarm Indication Signal with Customer Installation signature (AIS-CI)
•Remote Alarm Indication with Customer Installation (RAI-CI)
•Gapped Clock interface mode for Transmit and Receive.
•Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
•Parallel search algorithm for fast frame synchronization
•Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)
•Direct access to D and E channels for fast transmission of data link information
•PRBS, QRSS, and Network Loop Code generation and detection
•Programmable Interrupt output pin
•Supports programmed I/O and DMA modes of Read-Write access
•Each framer block encodes and decodes the T1/E1/J1 Frame serial data
•Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•Detects OOF, LOF, LOS errors and COFA conditions
•Loopbacks: Local (LLB) and Line remote (LB)
•Facilitates Inverse Multiplexing for ATM
•Performance monitor with one second polling
•Boundary scan (IEEE 1149.1) JTAG test port
•Accepts external 8kHz Sync reference
•1.8V Inner Core
•3.3V CMOS operation with 5V tolerant inputs
•225-pin PBGA package with -40 to +85 operation







Application

•High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
•SONET/SDH terminal or Add/Drop multiplexers (ADMs)
•T1/E1/J1 add/drop multiplexers (MUX)
•Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
•Digital Access Cross-connect System (DACs)
•Digital Cross-connect Systems (DCS)
•Frame Relay Switches and Access Devices (FRADS)
•ISDN Primary Rate Interfaces (PRA)
•PBXs and PCM channel bank
•T3 channelized access concentrators and M13 MUX
•Wireless base stations
•ATM equipment with integrated DS1 interfaces
•Multichannel DS1 Test Equipment
•T1/E1/J1 Performance Monitoring
•Voice over packet gateways
•Router





Specifications

Specifications
No. ofCH 2
DataRate(s) T1/E1/J1
Clk Rec Yes
SH/LH S/L
Temp.Range Ind.
OpPwr Sup/Max Cur 3.3V +/-5%
Pkgs BGA-225





Description

Description

The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R³ Technology™ (Reconfigurable, Relayless Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, The XRT86VL32 provides protection form power failures and hot swapping.

The XRT86VL32 contains an integral DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame the common DS1/E1/J1 signal formats. It also contains a transmit and overhead data input port for each channel, that permits data line terminal equipment direct access to the out-bound T1/E1/J1 frames. In the receive direction, it has complementary blocks to the transmit path.

The device is compliant with all T1/E1/J1 specifications including ANSI T1/E1.107-1998, ANSI T1/E1. 403-1995, ANSI T1/E1. 231-1993, ANSI T1/E1. 408-1990, AT&T TR 62411 (12-90) TR540616, and ITU G. 703, G. 704, G. 706, and G. 733. Also, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G. 703, JT G. 704, JT G. 706, I. 431.

R³ Technology™ Overview

Exar's breakthrough R³ Technology™ delivers key benefits to customers designing T1/E1/J1 interface cards. The devices are Reconfigurable with integrated termination supporting all common T1/E1/J1 line impedances enabling customers to build one board with a single bill-of-materials. Now, final device configuration can be done just prior to line-card installation. This unique capability prevents customers from having to unnecessarily stockpile an inventory of all configurations to accommodate changing market conditions. Also, the series employs Relayless Redundancy eliminating the need for external relays for 1:1 and 1+1 applications by establishing a back-up channel that can be brought on-line in the event of failure. The first application of this technology was multi-channel long-haul, short-haul (1, 4, and 8-channel) Line Interface Units (LIUs) that are already designed in at key customers in the targeted markets of Multi-Service Provisioning Platforms (MSPPs), access devices, media gateways, routers, and frame relay access devices.






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