XRT75R12

Features:

· R³ Technology (Reconfigurable, Relayless
Redundancy)
· On chip Clock and Data Recovery circuit for high
input jitter tolerance
· Meets E3/DS3/STS-1 Jitter Tolerance Requirement
· Detects and Clears LOS as per G.775
· Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
· On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
· On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
· Provides low jitter output clock
TRANSMITTER
· R³ Technology (Reconfigurable, Relayless
Redundancy)
· Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
· Tri-state Transmit output capability for redundancy
applications
· Each Transmitter can be turned on or off
· Transmitters provide Current Output Drive
JITTER ATTENUATOR
· On chip advanced crystal-less Jitter Attenuator for
each channel
· Jitter Attenuator can be selected in Receive,
Transmit path, or disabled
· Meets ETSI TBR 24 Jitter Transfer Requirements
· Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
· 16 or 32 bits selectable FIFO size
CONTROL AND DIAGNOSTICS
· Parallel Microprocessor Interface for control and
configuration
· Supports optional internal Transmit driver
monitoring
· Each channel supports Analog, Remote and Digital
Loop-backs
· Single 3.3 V ± 5% power supply
· 5 V Tolerant digital inputs
· Available in 420 pin TBGA Thermally enhanced
Package
· - 40°C to 85°C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
· Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
· Integrated Pulse Shaping Circuit
· Built-in B3ZS/HDB3 Encoder (which can be
disabled)
· Accepts Transmit Clock with duty cycle of 30%-
70%
· Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
· Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
· Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
· Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
· Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
· Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
· Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
· Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
· Declares Loss of Lock (LOL) Alarm
· Built-in B3ZS/HDB3 Decoder (which can be
disabled)
· Recovered Data can be muted while the LOS
Condition is declared
· Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment




Application

· E3/DS3 Access Equipment
· DSLAMs
· Digital Cross Connect Systems
· CSU/DSU Equipment
· Routers
· Fiber Optic Terminals




Specifications

Specifications
No. ofCH	12
DataRate(s)	DS3, E3, STS-1
Clk Rec	Yes
SH/LH	n/a
Temp.Range	Ind.
OpPwr Sup/Max Cur	3V ±5%
Pkgs	TBGA-420

SYMBOL	PARAMETER	MIN	MAX.	UNITS.	COMMENTS
VDD	Supply Voltage	-0.5	6.0	V	Note 1
VIN	Input current at any pin	-0.5	5.5	V	Note 1
VIN	Input current at any pin		100	mA	Note 1
STEMP	Storage Temperature	-65	150		Note 1
ATEMP	Ambient Operating Temperature	-40	85		linear airflow 0 ft./min
Theta JA	Thermal Resistance		23	/W	linear air flow 0ft/min (See Note 3 below)
MLEVL	Exposure to Moisture	5		level	EIA/JEDEC JESD22-A112-A
ESD	ESD Rating	2000		V	Note 2

NOTES:
1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair
reliability of the device.
2. ESD testing method is per MIL-STD-883D,M-3015.7
3. With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.




Description



Recognized for an already robust series of physical layer, access and metro products, Exar extends XRT75R12's capabilities by adding to the industry's first monolithic desynchronization solution for mapping/demapping from SONET/SDH (synchronous) to DS3/E3 (asynchronous), R³ Technology^TM.

Exar's R³ Technology^TM was first introduced in 2002 as a breakthrough capability delivering key benefits to customers designing interface cards. Devices utilizing the technology are Reconfigurable with integrated clock synthesizer supporting DS3/E3/STS-1 clock rates from a single clock source. This capability enables customers to build one board with a single bill-of-materials, and gives them the agility to quickly respond and reconfigure devices for compressed design cycles. In addition, the XRT75R12 series employs Relayless Redundancy eliminating the need for external relays for 1:1 and 1+1 applications by establishing a back-up channel that can be brought on-line in the event of failure.

The first T3/E3/STS-1 products to offer R³ Technology^TM are the XRT75R03D (three) and XRT75R12D (twelve) Previously, Exar has offered this capability only on its T1/E1 LIU products. Now customers doing T3/E3 designs can take advantage of this unique technology saving time and cost in implementing redundancy as well as supporting global standards for Telecom.

Product Highlights

The XRT75Rxx series has an independent receiver, transmitter and jitter attenuator in a single 52-pin TQFP package. XRT75R12 supports E3 (34.368.Mbps), DS3 (44.736Mbps) and STS-1 (51.84 Mbps) operations, has a differential receiver that provides a high noise interference margins -- capable of receiving data from cables of over 1,000 feet, or up to 12dB of cable attenuation. The device has an onboard Pseudo Random Binary Sequence (PRBS) generator and detector that can insert and detect single bit errors. This function is often used for diagnostic purposes. In addition, Exar adds desynchronization capability in its XRT75RxxD family.

What is Clock Desynchronization?

The process of mapping and subsequent de-mapping of DS3/E3 signals into SONET introduces excessive jitter and timing irregularities. Examples of jitter sources include mapping jitter, caused by bit justification, or stuffing, and pointer jitter, the outcome of frequency mismatches between networks that causes pointer movement. Current desynchronizing solutions use both a very narrow-bandwidth crystal oscillator based Phase Locked Loop (PLL) referred to as a Voltage Control Oscillator (VCXO), and a deep FIFO for each data rate and channel. For multi-channel/multi-rate applications, chip requirements can rise at exponential levels driven by the number of supported rates and channels. Enter Exar's solution; XRT75R12 uses only one highly integrated programmable PLL, now each channel can support multi-rate (DS3, E3 or STS-1) operations. Here jitter/timing irregularities are removed, and then desynchronized to provide a smooth GR-253-CORE specification-compliant clock signal. Once this operation is complete the signal is suitable for retransmission and returned to the data stream.

Standard's Compliance

The XRT75R12 receiver, transmitter, and jitter attenuator all meet Bellcore GR-499 CORE requirements. Also, the transmitter meets the GR-253 CORE and ANSI T1.102 specifications, and it includes a duty cycle correction PLL. The device meets jitter and wander specifications described in the T1.105.03b, and ETSI TBR-24, and is compliant with jitter transfer templates outlined in ITU G.751, G.752 and G.755.

The XRT75R12 is a twelve channel fully integrated Line Interface Unit (LIU) featuring EXAR's R3 Technology (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 12 independent Receivers, Transmitters and Jitter Attenuators in a single 420 Lead TBGA package. Each channel of the XRT75R12 can be independently configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tri-stated for redundancy support or for conserving power.

The XRT75R12's differential receiver provides high noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 dB of cable attenuation.

The XRT75R12 incorporates an advanced crystalless jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications.

The XRT75R12 provides a Parallel Microprocessor Interface for programming and control.

The XRT75R12 supports analog, remote and digital loop-backs. The device also has a built-in Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error for diagnostic purposes.