XRT75R03

Specifications

Specifications
No. ofCH	3
DataRate(s)	DS3, E3, STS-1
Clk Rec	Yes
SH/LH	n/a
Temp.Range	Ind.
OpPwr Sup/Max Cur	3V ±5%
Pkgs	TQFP-128

Specifications
No. ofCH	3
DataRate(s)	DS3, E3, STS-1
Clk Rec	Yes
SH/LH	n/a
Temp.Range	Ind.
OpPwr Sup/Max Cur	3V ±5%
Pkgs	TQFP-128

Description



Recognized for an already robust series of physical layer, access and metro products, Exar extends its capabilities by adding to the industry's first monolithic desynchronization solution for mapping/demapping from SONET/SDH (synchronous) to DS3/E3 (asynchronous), R³ Technology^TM. Exar's R³ Technology^TM was first introduced in 2002 as a breakthrough capability delivering key benefits to customers designing interface cards. XRT75Rxx Devices utilizing the technology are Reconfigurable with integrated clock synthesizer supporting DS3/E3/STS-1 clock rates from a single clock source. This capability  of XRT75Rxx enables customers to build one board with a single bill-of-materials, and gives them the agility to quickly respond and reconfigure devices for compressed design cycles. In addition, the series employs Relayless Redundancy eliminating the need for external relays for 1:1 and 1+1 applications by establishing a back-up channel that can be brought on-line in the event of failure.

The first T3/E3/STS-1 products to offer R³ Technology^TM are the XRT75Rxx (three) and XRT75R12D (twelve) Previously, Exar has offered this capability only on its T1/E1 LIU products. Now customers doing T3/E3 designs can take advantage of this unique technology saving time and cost in implementing redundancy as well as supporting global standards for Telecom.

Product Highlights

The XRT75Rxx series has an independent receiver, transmitter and jitter attenuator in a single 52-pin TQFP package. It supports E3 (34.368.Mbps), DS3 (44.736Mbps) and STS-1 (51.84 Mbps) operations, has a differential receiver that provides a high noise interference margins -- capable of receiving data from cables of over 1,000 feet, or up to 12dB of cable attenuation. The device has an onboard Pseudo Random Binary Sequence (PRBS) generator and detector that can insert and detect single bit errors. This function is often used for diagnostic purposes. In addition, Exar adds desynchronization capability in its XRT75RxxD family.

What is Clock Desynchronization?

The process of mapping and subsequent de-mapping of DS3/E3 signals into SONET introduces excessive jitter and timing irregularities. Examples of jitter sources include mapping jitter, caused by bit justification, or stuffing, and pointer jitter, the outcome of frequency mismatches between networks that causes pointer movement. Current desynchronizing solutions use both a very narrow-bandwidth crystal oscillator based Phase Locked Loop (PLL) referred to as a Voltage Control Oscillator (VCXO), and a deep FIFO for each data rate and channel of XRT75Rxx. For multi-channel/multi-rate applications, chip requirements can rise at exponential levels driven by the number of supported rates and channels. Enter Exar's solution; it uses only one highly integrated programmable PLL, now each channel of XRT75Rxx can support multi-rate (DS3, E3 or STS-1) operations. Here jitter/timing irregularities are removed, and then desynchronized to provide a smooth GR-253-CORE specification-compliant clock signal. Once this operation is complete the signal is suitable for retransmission and returned to the data stream.

Standard's Compliance

The receiver, transmitter, and jitter attenuator all meet Bellcore GR-499 CORE requirements. Also, the transmitter meets the GR-253 CORE and ANSI T1.102 specifications, and it includes a duty cycle correction PLL. The XRT75Rxx device meets jitter and wander specifications described in the T1.105.03b, and ETSI TBR-24, and is compliant with jitter transfer templates outlined in ITU G.751, G.752 and G.755.