XRT73LC03A

Features: • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03A• Meets E3/DS3/STS-1 Jitter Tolerance Requirements• Contains a 4-Wire Microprocessor Serial Interface• Full Loop-Back Capability• Transmit and Receive Power D...

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SeekIC No. : 004549462 Detail

XRT73LC03A: Features: • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03A• Meets E3/DS3/STS-1 Jitter Tolerance Requirements• Contains a 4-Wire ...

floor Price/Ceiling Price

Part Number:
XRT73LC03A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/9

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Product Details

Description



Features:

• Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03A
• Meets E3/DS3/STS-1 Jitter Tolerance Requirements
• Contains a 4-Wire Microprocessor Serial Interface
• Full Loop-Back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Uses Minimum External components
• Single +3.3V Power Supply
• Low power CMOS design
• 5V tolerant I/O
• -40°C to +85°C Operating Temperature Range
• Available in a 120 pin LQFP package





Application

• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
• Multiplexers
• ATM Switches





Pinout

  Connection Diagram




Specifications

Specifications
No. ofCH 3
DataRate(s) DS3, E3, STS-1
Clk Rec Yes
SH/LH n/a
Temp.Range Ind.
OpPwr Sup/Max Cur 3V
Pkgs TQFP-120


Storage Temperature.......................... - 65 to + 150
Operating Temperature .........................- 40 to + 85
Supply Voltage Range .........................-0.5V to +3.465V
Theta-JA .............................................................25/W
Theta-JC ............................................................8.5/W
NOTE: The XRT73LC03A is assembled in a thermally enhanced package with an integral Copper Heat Slug. The Heat Slug is solder plated and is exposed on the bottom of the package and is electrically connected to the internal GND connections of the device. This Heat Slug can be soldered to the mounting board if desired, but must be electrically isolated from any VDD connections.






Description



The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73LC03A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer.

In the receive direction, the XRT73LC03A performs equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations.



The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.

Each channel of the XRT73LC03A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels.

In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer.

In the receive direction, the XRT73LC03A performs equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations.






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