Specifications Specifications CH 1 CPUInterface VLIO Data Rate@5/3.3/2.5V na/20/16 Tx/RxFIFO(Bytes) 32/32 Tx/RxFIFOCtrs Yes Tx/RxFIFOINT Trig 4 Levels/ 4 Levels AutoRTS/CTS Yes IrDaSup Yes 5VTolInputs No Sup V 1.62-3.63 Pkgs BGA-25, QFN-24, QFN-32De...
XR16M681: Specifications Specifications CH 1 CPUInterface VLIO Data Rate@5/3.3/2.5V na/20/16 Tx/RxFIFO(Bytes) 32/32 Tx/RxFIFOCtrs Yes Tx/RxFIFOINT Trig 4 Levels/ 4 Levels AutoR...
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Specifications | |
CH | 1 |
CPUInterface | VLIO |
Data Rate@5/3.3/2.5V | na/20/16 |
Tx/RxFIFO(Bytes) | 32/32 |
Tx/RxFIFOCtrs | Yes |
Tx/RxFIFOINT Trig | 4 Levels/ 4 Levels |
AutoRTS/CTS | Yes |
IrDaSup | Yes |
5VTolInputs | No |
Sup V | 1.62-3.63 |
Pkgs | BGA-25, QFN-24, QFN-32 |
The XR16M681¹ (M681) is an enhanced Universal Asynchronous Receiver and Transmitter (UART) with a VLIO bus interface and has 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 20 Mbps at 3.3V, 16 Mbps at 2.5V and 10 Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control feature simplifies both the hardware and software for half-duplex RS-485 applications. In addition, the Multidrop mode with Auto Address detection increases the performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator feature allows the transmitter and receiver to operate at different baud rates. Power consumption of the M681 can be minmized by enabling the sleep mode and PowerSave mode.
The XR16M681 has a 16550 compatible register set that provide users with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M681 is available in 24-pin QFN, 32-pin QFN and 25-pin BGA packages.
NOTE: ¹Covered by U.S. Patent #5,649,122.