Features: Added feature in devices with top mark date code of F2 YYWW and newer:`5 volt tolerant inputs-2.97 to 5.5 Volt Operation- Pin-to-pin compatible with the industry standard ST16C554 andST16C654 and TI's TL16C554N and TL16C754BFN-Intel or Motorola Data Bus Interface select-Four independen...
XR16C864: Features: Added feature in devices with top mark date code of F2 YYWW and newer:`5 volt tolerant inputs-2.97 to 5.5 Volt Operation- Pin-to-pin compatible with the industry standard ST16C554 andST1...
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Specifications | |
CH | 4 |
CPUInterface | Intel or Motorola |
Data Rate@5/3.3/2.5V | 2.0/1.5/na |
Tx/RxFIFO(Bytes) | 128/128 |
Tx/RxFIFOCtrs | Yes |
Tx/RxFIFOINT Trig | Program/ Program |
AutoRTS/CTS | Yes |
IrDaSup | Yes |
5VTolInputs | Yes |
Sup V | 2.97-5.5 |
Pkgs | QFP-100 |
The XR16C8641 (864) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 128 bytes of transmit and receive FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow control, automatic RS-485 half-duplex direction control and data rates of up to 2 Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. System interrupts may be tailored to meet design requirements. An internal loopback capability allows onboard diagnostics. The 864 is available in the 100- pin QFP package. The XR16C864 offers faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a separate clock input for channel C (CHCCLK). The XR16C864 is compatible with the industry standard ST16C554/554D, ST16C654/654D and XR16C854/854D.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.