XIO2000A

· Full x1 PCI Express Throughput
· Fully Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
· Fully Compliant with PCI Express Base Specification, Revision 1.0a
· Fully Compliant with PCI Local Bus Specification, Revision 2.3
· Extended Virtual Channel (VC) Support Includes a Second VC for Quality-of-Service and Isochronous Applications
· PCI Express Advanced Error Reporting Capability Including ECRC Support
· Support for D1, D2, D3hot, and D3cold
· Active State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
· Wake Event and Beacon Support
· Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
· Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
· Robust Pipeline Architecture To Minimize Transaction Latency
· Full PCI Local Bus 66-MHz/32-Bit Throughput
· Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Leve  Prioritization Scheme
· Low Power Design (<350 mW) Ensures Ease of Implementation
· Two Package Options: 15 mm x 15 mm and 12 mm x 12 mm
· Internal PCI Arbiter Supporting Up to 6 External PCI Masters
· Advanced VC Arbitration Options Include VC1 Strict Priority, Hardware-Fixed Round-Robin, and 32-Phase, Weighted Round-Robin
· Advanced PCI Bus Port Arbitration Options Include 128-phase, Weighted Round-Robin Time-Based and 128-phase, Weighted Round-Robin Aggressive Time-Based
· Advanced PCI Isochronous Windows for Memory Space Mapping to a Specified Traffic Class
· Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts from CardBus Applications
· External PCI Bus Arbiter Option
· PCI Bus LOCK Support
· Clock Run and Power Override Support
· Six Buffered PCI Clock Outputs (33 MHz or 66 MHz)
· PCI Bus Interface 3.3-V and 5.0-V (33 MHz only at 5.0 V) Tolerance Options
· Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
· Eight 3.3-V, Multifunction, General-Purpose I/O Terminals
· Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
· Compact Footprint, 201-Ball, GZZ MicroStarTM BGA or Lead-Free 201-Ball, ZZZ MicroStarTM BGA

Supply voltage range: V_{DD_33} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
V_{DD_15} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .   ..  . . .0.5 V to 1.65 V
V_CCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . . . . . . .0.5 V to 5.25 V
Input voltage range, V_I: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CCP + 0.5 V
V_I: PCI Express (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .. . . . . . . . .0.6 V to 0.6 V
V_I: PCI Express REFCLK (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V toV_{DD_33} + 0.5 V
V_I: PCI Express REFCLK (differential) . . . . . . . . . . . . . .  . . . .. . . . . . . . . . . .  . . . .  0.5 V toV_{DD_15} + 0.5 V
V_I: Miscellaneous 3.3-V I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_{DD_33} + 0.5 V
Output voltage range: V_O: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V_{DD_33} + 0.5 V
V_O: PCI Express (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_{DD_15} + 0.5V
V_O: Miscellaneous 3.3-V IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V_{DD_33} + 0.5 V
Input clamp current, (V_I < 0 or V_I > V_DD) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, (V_O < 0 or V_O > V_DD) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Human body model (HBM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500 V
Charged device model (CDM) ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 to 150
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V_I < 0 or V_I > V_DD or V_I > V_CCP.
2. Applies to external output and bidirectional buffers. V_O < 0 or V_O > V_DD or V_O > V_CCP.

The XIO2000A is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC). For upstream traffic, up to six posted and four nonposted transactions are simultaneously supported for each VC.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 1.0a.

The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting capability including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully utilize both of these features.

Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are detected, then packet poisoning is supported for both upstream and downstream operations.

The PCI XIO2000A local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model.

The PCI bus interface XIO2000A is 32-bit and can operate at either 33 MHz or 66 MHz. Also, the PCI interface provides fair arbitration and buffered clock outputs for up to 6 subordinate devices. The bridge has advanced VC arbitration and PCI port arbitration features for upstream traffic. When these arbitration features are fully utilized, bridge throughput performance may be tuned for a variety of complex applications.

Power management (PM) XIO2000A features include active state link PM, PME mechanisms, the beacon and wake protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK messages are supported. Standard PCI bus power management features provide several low power modes, which enable the host system to further reduce power consumption.

The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial EEPROM, power override, clock run, and PCI bus LOCK. Also, eight general-purpose inputs and outputs (GPIOs) are provided for further system control and customization.