XCR3512XL:

Features: • Lowest power 512 macrocell CPLD• 7.5 ns pin-to-pin logic delays• System frequencies up to 127 MHz• 512 macrocells with 12,800 usable gates• Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (...

product image

XCR3512XL: Picture
SeekIC No. : 004548132 Detail

XCR3512XL:: Features: • Lowest power 512 macrocell CPLD• 7.5 ns pin-to-pin logic delays• System frequencies up to 127 MHz• 512 macrocells with 12,800 usable gates• Available in sma...

floor Price/Ceiling Price

Part Number:
XCR3512XL:
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/21

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• Lowest power 512 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 127 MHz
• 512 macrocells with 12,800 usable gates
• Available in small footprint packages
- 208-pin PQFP (180 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (260 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- FZP™ CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for architecture description



Description

The XCR3512XL: is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,800 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Motors, Solenoids, Driver Boards/Modules
Optical Inspection Equipment
Cables, Wires - Management
Tapes, Adhesives
803
Static Control, ESD, Clean Room Products
View more