XCR3320: 320

The XCR3320 device is a member of the CoolRunner® family of high-density SRAM-based CPLDs (Complex Pro- grammable Logic Device) from Xilinx. This device com- bines high speed and deterministic pin-to-pin timing with high density. The XCR3320 uses the patented Fast Zero Power (FZP™) design technique that combines high speed and low power for the first time ever in a  CPLD.  FZP  allows  the  XCR3320  to have true pin-to-pin timing delays of 7.5
ns, and standby currents of 100 µA without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used since the bipolar era) with a cascaded chain of pure CMOS gates, both standby and dynamic power are dramatically reduced when compared to other CPLDs. The FZP design tech-nique is also what allows Xilinx to offer a true CPLD archi-tecture in a high density device.

The Xilinx XCR3320 devices use the patented XPLA2 (eXtended Programmable Logic Array) architecture. This architecture combines the best features of both PAL- and PLA-type logic structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA2 architecture is constructed from 80 macrocell Fast Modules that are connected together by an interconnect array. Within each Fast Module are four Logic Blocks of 20 macrocells each. Each Logic Block contains a PAL structure with four dedi-cated product terms for each macrocell. In addition, each Logic Block has 32 additional product terms in a PLA struc- ture that can be shared through a fully programmable OR array to any of the 20 macrocells. This combination effi-ciently allocates logic throughout the Logic Block, which increases device density and allows for design changes without re-defining the pinout or changing the system tim-ing. The XCR3320 offers pin-to-pin propagation delays of 7.5 ns through the PAL array of a Fast Module; and if the PLA array is used, an additional 1.5 ns is added to the delay, no matter how many PLA product terms are used. If the interconnect array between Fast Modules is used, there is a second fixed delay of 2.0 ns. This means that the worst case pin-to-pin propagation delay within a fast module is 7.5 + 1.5 = 9.0 ns, and the delay from any pin to any other pin across the entire chip is 7.5 + 2.0 = 9.5 ns if only the PAL array is used, and 7.5 + 1.5 + 2.0 = 11.0 ns if the PLA array is used.

Each macrocell also has a two input XOR gate with the dedicated PAL product terms on one input and the PLA product terms on the other input. This patent-pending Ver-satile XOR structure allows for very efficient logic optimiza-tion compared to competing XOR structures that have only one product term as the second input to the XOR gate. The Versatile XOR allows an 8-bit XOR function to be imple-mented in only 20 product terms, compared to 65 product terms for the traditional XOR approach.

The XCR3320 is SRAM-based, which means that it is con-figured from an external source at power up. See the con-figuration section of this data sheet for more information. The device supports the full JTAG specification (IEEE 1149.1) through an industry standard JTAG interface. It can also be configured through the JTAG port, which is very useful for prototyping. See section titled "Device Configura-tion Through JTAG" on page 29 for more information.