XCR3256XL

Features: • Lowest power 256 macrocell CPLD• 7.5 ns pin-to-pin logic delays• System frequencies up to 140 MHz• 256 macrocells with 6,000 usable gates• Available in small footprint packages - 144-pin TQFP (120 user I/O pins) - 208-pin PQFP (164 user I/O) - 256-ball FBG...

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SeekIC No. : 004548128 Detail

XCR3256XL: Features: • Lowest power 256 macrocell CPLD• 7.5 ns pin-to-pin logic delays• System frequencies up to 140 MHz• 256 macrocells with 6,000 usable gates• Available in smal...

floor Price/Ceiling Price

Part Number:
XCR3256XL
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Lowest power 256 macrocell CPLD
• 7.5 ns pin-to-pin logic delays
• System frequencies up to 140 MHz
• 256 macrocells with 6,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (120 user I/O pins)
- 208-pin PQFP (164 user I/O)
- 256-ball FBGA (164 user I/O)
- 280-ball CS BGA (164 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power™ (FZP) CMOS design technology
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for architecture description



Description

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz.




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