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XCR3064XL

Features: • 6.0 ns pin-to-pin logic delays• System frequencies up to 145 MHz• 64 macrocells with 1,500 usable gates• Available in small footprint packages - 44-pin VQFP (36 user I/O pins) - 48-ball CS BGA (40 user I/O pins) - 56-ball CP BGA (48 user I/O pins) - 100-pin TQFP...

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SeekIC No. : 004548121 Detail

XCR3064XL: Features: • 6.0 ns pin-to-pin logic delays• System frequencies up to 145 MHz• 64 macrocells with 1,500 usable gates• Available in small footprint packages - 44-pin VQFP (36 u...

XCR3064XL Data Sheet

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Part Number:
XCR3064XL
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin TQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five metal layer reprogrammable process
- FZP™ CMOS design technology- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per logic block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per logic block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V industrial temperature range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for architecture description
• Advanced system features


Description

The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four logic blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.




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