XCR3064XL-10CP56C

Voltage Supply - Internal: 3 V ~ 3.6 V
Mounting Type: Surface Mount
Packaging: Tray
Number of Logic Elements/Blocks: 4
Number of Macrocells: 64
Operating Temperature: 0°C ~ 70°C
Number of I /O: 48
Programmable Type: In System Programmable (min 1K program/erase cycles)
Manufacturer: Xilinx Inc
Number of Gates: 1500
Package / Case: 56-LFBGA, CSPBGA
Supplier Device Package: 56-CSBGA (6x6)
Series: CoolRunner XPLA3
Delay Time tpd(1) Max: 9.1ns


Features:

• Lowest power 64 macrocell CPLD
• 6.0 ns pin-to-pin logic delays
• System frequencies up to 145 MHz
• 64 macrocells with 1,500 usable gates
• Available in small footprint packages
- 44-pin PLCC (36 user I/O pins)
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
• Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power™ (FZP) CMOS design technology
• Advanced system features- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for dual function of JTAG ISP pins
• 2.7V to 3.6V supply voltage at industrial temperature range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012) for architecture description


Description

The XCR3064XL-10CP56C is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.