XC9572XL Selling Leads, Price trend, XC9572XL DataSheet download, circuit diagram from SeekIC.com

Features: • 5 ns pin-to-pin logic delays• System frequency up to 178 MHz• 72 macrocells with 1,600 usable gates• Available in small footprint packages- 44-pin PLCC (34 user I/O pins)- 44-pin VQFP (34 user I/O pins)- 48-pin CSP (38 user I/O pins)- 64-pin VQFP (52 user I/O pi...

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SeekIC No. : 004548090 Detail

XC9572XL: Features: • 5 ns pin-to-pin logic delays• System frequency up to 178 MHz• 72 macrocells with 1,600 usable gates• Available in small footprint packages- 44-pin PLCC (34 user I...

XC9572XL Data Sheet

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Part Number:: XC9572XL
Supply Ability:: 5000

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Upload time: 2024/12/21

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Product Details

Description

Features:

• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS FastFLASH™ technology
• Advanced system features- In-system programmable- Superior pin-locking and routability with FastCONNECT II™ switch matrix- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package

Specifications

Symbol	Description	Value	Units
V_CC	Supply voltage relative to GND	0.5 to 4.0	V
V_IN	Input voltage relative to GND⁽¹⁾	0.5 to 5.5	V
V_TS	Voltage applied to 3-state output⁽¹⁾	0.5 to 5.5	V
T_STG	Storage temperature (ambient)	65 to +150
T_SOL	Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)	+260
T_J	Junction temperature	+150

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to 2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability

Description

The XC9572XL is a 3.3V CPLD targeted for high-performance,low-voltage applications in leading-edge communications and computing systems. XC9572XL is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview.

XC9572XL

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