XC9572-15TQG100I

Mounting Type: Surface Mount
Packaging: Tray
Programmable Type: In System Programmable (min 10K program/erase cycles)
Delay Time tpd(1) Max: 15.0ns
Operating Temperature: -40°C ~ 85°C
Number of Logic Elements/Blocks: 4
Voltage Supply - Internal: 4.5 V ~ 5.5 V
Package / Case: 100-LQFP
Supplier Device Package: 100-TQFP (14x14)
Manufacturer: Xilinx Inc
Number of Macrocells: 72
Number of Gates: 1600
Number of I /O: 72
Series: XC9500


Description

The XC9572-15TQG100I is designed as one kind of high-performance CPLD that is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns, and it is providing advanced in-system programming and test capabilities for general purpose logic integration.

Features of the XC9572-15TQG100I are:(1)7.5 ns pin-to-pin logic delays on all pins;(2)fCNT to 125 MHz;(3)72 macrocells with 1,600 usable gates;(4)Up to 72 user I/O pins;(5)Enhanced pin-locking architecture;(6)Extensive IEEE Std 1149.1 boundary-scan (JTAG) support;(7)Programmable power reduction mode in each macrocell;(8)Slew rate control on individual outputs;(9)User programmable ground pin capability;(10)Extended pattern security features for design protection;(11)High-drive 24 mA outputs;(12)Advanced CMOS 5V FastFLASH technology;(13)Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages;(14)3.3 V or 5 V I/O capability.

The absolute maximum ratings of the XC9572-15TQG100I can be summarized as:(1)Supply voltage relative to GND: -0.5 to 7.0 V;(2)DC input voltage relative to GND: -0.5 to VCC + 0.5 V;(3)Voltage applied to 3-state output with respect to GND: -0.5 to VCC + 0.5 V;(4)Storage temperature: -65 to +150 °C;(5)Max soldering temperature (10 s @ 1/16 in = 1.5 mm): +260 °C.

The electrical characteristics of XC9572-15TQG100I can be summarized as:(1)I/O to output valid: 15.0 ns;(2)I/O setup time before GCK: 8.0 ns;(3)I/O hold time after GCK: 0.0 ns;(4)GCK to output valid: 8.0 ns;(5)16-bit counter frequency: 95.2 MHz;(6)Multiple FB internal operating frequency: 55.6 MHz;(7)I/O setup time before p-term clock input: 4.0 ns;(8)I/O hold time after p-term clock input: 4.0 ns;(9)GCK pulse width (High or Low): 5.5 ns;(10)GTS to output disable: 11.0 ns. If you want to know more information such as the electrical characteristics about XC9572-15TQG100I, please download the datasheet in www.seekic.com or www.chinaicmart.com.