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XC95108

Features: • 7.5 ns pin-to-pin logic delays on all pins• fCNT to 125 MHz• 108 macrocells with 2400 usable gates• Up to 108 user I/O pins• 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temper...

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XC95108: Features: • 7.5 ns pin-to-pin logic delays on all pins• fCNT to 125 MHz• 108 macrocells with 2400 usable gates• Up to 108 user I/O pins• 5 V in-system programmable (ISP...

XC95108 Data Sheet

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Part Number:
XC95108
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 108 macrocells with 2400 usable gates
• Up to 108 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP and 160-pin PQFP packages


Specifications

Symbol Parameter Value Units
VCC Supply voltage relative to GND -0.5 to 7.0 V
VIN DC input voltage relative to GND -0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC + 0.5 V
TSTG Storage temperature -65 to +150
TSOL Max soldering temperature (10s @ 1/16 in = 1.5 mm) +260



Description

The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.




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