XC7272A

The XC7272A combines the classical features of the PAL-like CPLD architecture with innovative systems-oriented logic enhancements.This favors the implementation of fast state machines, large synchronous counters and fast arithmetic, as well as multi-lelvel general-purpose logic.Performance, measured in achievable system clock rate and ciritical delays, is not only predictate routing, and resource utilization.Performance, therefore, remians invariant between design iterations.The propagation delay through interconnect and logic is constant for any function impelented in any one of the output macrocells.

Features of of the XC7272A are:(1)second-generation high density programmablel ogic device; (2)UV-erasable CMOS EPROM technology; (3)each FB contains a programmable AND-array with 21 complementary inputs, providing up to 16 product terms per macrocell; (4)indentical timing for all interconnect paths andfor all macrocell logic paths; (5)I/O-pin is useable as input when macrocell is buried; (6)two high-speed, low-skew global clock inputs; (7)availablei n 68-pin and 84-pin PLCC/CLCC,84-pin PGA packages.

The absolute maximum ratings of the XC7272A can be summarized as:(1): supply voltage with respect to GND(Vcc) is -0.5 V to Vcc+0.5 V; (2): DC input voltage with respect to GND(VIN) is -0.5 V to Vcc+0.5 V; (3): voltage applied to 3-state output with repect to GND(VTS) is -0.5 V to 7.0 V; (4): storage temperature(Tstg) is -65 to +150; (5): maximum soldering temperature(Tsol) is 260(10s at 1/16in=1.5mm).

The recommended operating conditions of the XC7272A can be summarized as:(1): supply voltage relative to GND commercial is 4.75 V min and 5.25 V max(Ta is 0 to 70); (2): supply voltage relative to GND industrial is 4.5 V min and 5.5 V max(Ta is -40 to 85); (3): supply voltage relative to GND military is 4.5 V min and 5.5 V max(Ta is -40 to 85); (4): high-level input voltage(VIH) is 2.0 V min and Vcc+0.5 V max; (5): low-level input voltage(VIL) is 0 V min and 0.8 V max.