Features: .Low-cost, register/latch rich, SRAM based reprogrammable architecture- 0.5m m three-layer metal CMOS process technology- 256 to 1936 logic cells (3,000 to 23,000 gates )- Price competitive with Gate Arrays.System Level Features- System performance beyond 50 MHz- 6 levels of interconne...
XC5200 Series: Features: .Low-cost, register/latch rich, SRAM based reprogrammable architecture- 0.5m m three-layer metal CMOS process technology- 256 to 1936 logic cells (3,000 to 23,000 gates )- Price competit...
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Symbol |
Description |
|
Units |
VCC |
Supply voltage relative to GND |
-0.5 to +7.0 |
V |
VIN |
Input voltage with respect to GND |
-0.5 to VCC +0.5 |
V |
VTS |
Voltage applied to 3-state output |
-0.5 to Vcc +0.5 |
V |
TSTG |
Storage temperature (ambient) |
-65 to +150 |
C |
TSOL |
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) |
+260 |
C |
|
Junction temperature in plastic packages |
+125 |
C |
Junction temperature in ceramic packages |
+150 |
C |
The XC5200 Field-Programmable Gate Array Family is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA fami- lies, the XC5200 family brings a robust feature set to pro-(TM) grammable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of inter-connect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar Xilinx soft- ware environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, sche- matic capture, VHDL, and Verilog HDL synthesis. Design- ers utilizing logic synthesis can use their existing tools to design with the XC5200 devices.