Features: • Industry First Platform FPGA Solution• IP-Immersion Architecture- Densities from 40K to 8M system gates- 420 MHz internal clock speed (Advance Data)- 840+ Mb/s I/O (Advance Data)• SelectRAM™ Memory Hierarchy- 3 Mb of dual-port RAM in 18 Kbit block SelectRAM reso...
XC2V1000: Features: • Industry First Platform FPGA Solution• IP-Immersion Architecture- Densities from 40K to 8M system gates- 420 MHz internal clock speed (Advance Data)- 840+ Mb/s I/O (Advance D...
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Symbol | Description |
Conditions |
Units |
VCCINT VCCAUX VCCO VBATT VREF VIN(3) VTS TSTG TSOL TJ |
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage Input voltage relative to GND (user and dedicated I/Os) Voltage applied to 3-state output (user and dedicated I/Os) Storage temperature (ambient) Maximum soldering temp. Operating junction temperature (2) |
0.5 to 1.65 0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 0.5 to VCCO + 0.5 0.5 to VCCO + 0.5 0.5 to 4.0 65 to +150 +220 +125 |
V V V V V V V °C °C °C |
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website.
3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the device is not PCI compliant.
The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules.
The Virtex-II family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, the Virtex-II family comprises 11 members, ranging from 40K to 8M system gates.