XC2S50-5TQG144C

IC SPARTAN-II FPGA 50K 144-TQFP

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SeekIC No. : 003506540 Detail

XC2S50-5TQG144C: IC SPARTAN-II FPGA 50K 144-TQFP

floor Price/Ceiling Price

US $ 7.71~7.71 / Piece | Get Latest Price
Part Number:
XC2S50-5TQG144C
Mfg:
Supply Ability:
5000

Price Break

  • Qty
  • 0~1
  • Unit Price
  • $7.71
  • Processing time
  • 15 Days
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Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Quick Details

Series: Spartan®-II Manufacturer: Xilinx Inc
Number of LABs/CLBs: 384 Number of Logic Elements/Cells: 1728
Total RAM Bits: 32768 Number of I /O: 92
Number of Gates: 50000 Operating Supply Voltage : 50 V
Voltage - Supply: 2.375 V ~ 2.625 V Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C Package / Case: 144-LQFP    

Description

Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C
Package / Case: 144-LQFP
Supplier Device Package: 144-TQFP (20x20)
Voltage - Supply: 2.375 V ~ 2.625 V
Number of I /O: 92
Number of Logic Elements/Cells: 1728
Manufacturer: Xilinx Inc
Number of Gates: 50000
Series: Spartan®-II
Number of LABs/CLBs: 384
Total RAM Bits: 32768


Description

XC2S50-5TQG144C belongs to the Spartan-II FPGA family. There is some information about the Spartan-II FPGA family as follows.

The Spartan-II family of FPGA (Field-Programmable Gate Array) have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels. They are ideal for shortening product development cycles while offering a cost-effective solution for high volume production.

There are some features of Spartan-II FPGA family . First, it adopts second generation ASIC replacement technology with unlimited reprogrammability, very low cost and cost-effective 0.18 micron process. It densities 5,292 logic cells with up to 200,000 system gates. The second is system level features. It is fully PCI compliant and has low-power segmented routing architecture. Besides, it has full readback ability for verification/observability, cascade chain for wide-input functions, four dedicated DLLs for advanced clock control and four primary low-skew global clock distribution nets. The last one is core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V.

What comes next is about the absolute maximum ratings of Spartan-II FPGA family . The VCCINT (supply voltage relative to GND) is from -0.5 to 3.0 V. The VCCO (supply voltage relative to GND) is from -0.5 to 4.0 V. The VREF (input reference voltage) is from -0.5 to 3.6 V. The VIN (input voltage relative to GND) is from -0.5 to 5.5 V when 5 V tolerant I/O and from -0.5 to VCCO+0.5 V when no 5 V tolerance. The VTS (voltage applied to 3-state output) is from -0.5 to 5.5 V when 5 V tolerant I/O and from -0.5 to VCCO+0.5 V when no 5 V tolerance. The TSTG (storage temperature (ambient)) is from -65 to +150. The TJ (junction temperature) is +125.




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