XC2S200-5PQ208C

Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C
Package / Case: 208-BFQFP
Supplier Device Package: 208-PQFP (28x28)
Number of I /O: 140
Voltage - Supply: 2.375 V ~ 2.625 V
Manufacturer: Xilinx Inc
Series: Spartan®-II
Number of Gates: 200000
Number of LABs/CLBs: 1176
Number of Logic Elements/Cells: 5292
Total RAM Bits: 57344


Description

XC2S200-5PQ208C belongs to the Spartan-II FPGA family. There is some information about the Spartan-II FPGA family as follows.

The Spartan-II family of FPGA (Field-Programmable Gate Array) XC2S200-5PQ208C have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels.

The Spartan-II family of FPGA XC2S200-5PQ208C are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. The typical applications include high-volume fields where the versatility of a fast programmable solution adds benefits.

There are some features of XC2S200-5PQ208C. First, it adopts second generation ASIC replacement technology with unlimited reprogrammability, very low cost and cost-effective 0.18 micron process. It densities 5,292 logic cells with up to 200,000 system gates. The second is system level features. It is fully PCI compliant and has low-power segmented routing architecture. Besides, it has full readback ability for verification/observability, cascade chain for wide-input functions, four dedicated DLLs for advanced clock control and four primary low-skew global clock distribution nets. Then is versatile I/O and packaging consisting of low cost packages available in all densities, family footprint compatibility in common packages, 16 high-performance interface standards, hot swap Compact PCI friendly and zero hold time simplifies system timing. At last, it is fully supported by powerful Xilinx development system.